perm filename MAPPLX.JBR[MPX,SYS] blob
sn#699495 filedate 1976-06-07 generic text, type C, neo UTF8
COMMENT ⊗ VALID 00013 PAGES
C REC PAGE DESCRIPTION
C00001 00001
C00003 00002 Microprocessor Data Paths Diagram
C00012 00003 Micro Instruction Data Paths Diagram
C00016 00004 Device and Memory Data Paths
C00021 00005 Registers and Tables
C00030 00006 Microword Formats
C00037 00007 I/O Bus Interface
C00040 00008 Mappiplexor Bus Interface
C00045 00009 MAPPIPLEXOR BUS - QUICKLATCH CONNECTOR
C00049 00010 Error Conditions
C00050 00011 Detailed Logic Description - Microprocessor Data Paths and Registers
C00057 00012 Detailed Logic Description - I/O BUS Interface
C00059 00013 Detailed Logic Description - Clock Generation
C00060 ENDMK
C⊗;
Microprocessor Data Paths Diagram
------
| |
/ | SEL | /
-SEL /---| BUS |/------------------------------------------------------------\
BUS \---| REG |\--\ /----------------------\ /-----------------------\ |
4,2,1 \ | 3-S | \ | | | | | |
| | | | ---------------------------- | |
------ | | | | | |
| | | ALU | | |
------ | | | A B | | |
MA HI| | | | ---------------------------- | |
/ | | | | / \ / \ | |
PADR /---| | / / | /| |\ /| |\ | |
14:26 \---| PADR |/--- | | | | \-------------\ | |
\ | |\---\ | ---------------- \-------------\ | | |
| 14:35| \ | | / \ | | | |
| | | | / \ | | | |
| REG | | | -------------------- | | | |
MA LO| | | | / \ / \ | | | |
/ | 3-S | / | | /| |\ /| |\ | | | |
PADR /---| |/---/ | | | | | | | | |
27:35 \---| |\---\ | -CONSTANT FROM | | | | | |
\ | | \ | | MICROCODE | | | | | |
| | | | | | | | | |
------ | | ---------------------------------- | | | |
| | | MASK 0:15 | | | | |
------ | | | | | | | |
| | | | | 16 BIT MASKER | | | | |
TO VBIT/ | ALU | / | | | | | | | |
ABIT, /---| |/--/ | ---------------------------------- | | | |
MAPRAM\---|LATCH |\-----/ / \ / \ / \ | | | |
INPUTS \ | | \ /| |\ /| |\ /| |\ | | | |
| 0:15 | | | | | | | | | | |
| | ---------- ---------- | | | | | |
------ | R 0:15 | | M 0:15 | | \-----/ | | |
| 16 BIT | | MASK | | /--------/ | |
| ROTATE | | GENERATE | | | | |
---------- ---------- ---------- | |
/ \ / B 0:15 \ | |
/| |\ / \ | |
| | -------------- | |
| | / \ / \ | |
| | /| |\ /| |\ | |
| | | | | | | |
| | AR 0:15 BR 0:15 | |
-------------------------------------------------------------------- | |
/ S 0:15 \ | |
/ \ | |
/ \ | |
-------------------------------------------------------------------------- | |
/ \ / \ / \ / \ / \ / \ / \ / \ | |
/| |\/| |\/| |\ /| |\ /| |\ /| |\ /| |\ /| |\ | |
/ | | | | | | | | | | | | | | | | |
* MS| |MS| |MS| -VBIT NEW -VBIT ------------ ---------- ---------- | |
------------------- BIT 0:15 0:15 | 8 X 13 || AR 0:15 | | BR 0:15 || |
/0:3 4:19 20:35 \ | PAGE TABLE || 16 BIT | | 16 BIT || |
/ SELECT AND LATCH \ | POINTER || REG | | REG || |
----------------------- | RAM | ---------- ---------- | |
/ \ / \ -----/\----- / \ / \ | |
/| |\ /| |\ \/ /| |\ /| |\ | |
| | | | / \ | | | | | |
MEMDON D ------------ /| |\ | | | | | |
0:35 | I 0:35 | | | | | | | | |
| 36 BIT | | \---------/ \---------/ \----/ |
| REG | \------------------------------------/
-MICRO MEM SEL -->|AND|-->MAPC MAP
RQ 7 -->| SOLVER | ------- -->| |
| |---> CYCLE TIMING | 1 x 8 |--/ ---
MCYC MEM| | SEL BUS --\| MAP |
RQ -->| | 4,2,1 --/| ENB |
-------- | RAM |
-------
-------
--------- | |
DEV 0 ->| DATA |---\ PDATA D 0:35 |3-STATE|
. | XCVR |---/ PDATA PAR FROM --\| |--\ SEL BUS 4,2,1
. | WITH | MICROPROCESSOR --/|DRIVERS|--/ PADR 20:26
. | TO DEV |/--- MEMDON D 0:35 | |
DEV 7 ->| LATCH |\--- MEMDON PAR | |
--------- 8[WO≤ / \
/| |\
| |
/---------------/ \---------------\
| |
| /---------------------------\ |
| | | |
|\ | | | |
\ | \ --------------------- ---------------------
AR ----\| \ 0:2 \ | | | |
8:15 ----/| \ --------\| IRAM 0:31 | | IRAM 0:31 |
/ | |--------/| | | |
|MPC | / | 256 WORD RAM | | 32 WORD ROM |
----- | A | 3:7 \ | | \ | |
\ |8 BIT|MPC\ | |--------\| |--------\| |
IR ---\| PC |----\| / --------/ ---------/\---------- --------/ ---------------------
23:30---/|CNTR |----/| / / \/ /
/ | | / | / / \
----- |/ /| |\
| |
MS 4:35
Device and Memory Data Paths
-------
DEV 0 ->| ADDR |
. | 14:35 | PADR 18:19
. | AND |---\ PADR 14-35, PADR WRITE | |
. |CONTROL|---/ PADR SUPRESS MAPPING \| |/
. |SELECT | \ /
DEV 7 ->|(3-S) | --------- ---
-∧---∧- | COMPARE |=---->| |--\ MATCH
-PRIOR | | --------- /->|AND|--/ ---
MICRO MEM-/ | / \ | --- -------------->| |
SEL | / | | \ | /-------/ --¬ |AND|-->ACCESS OK
| | | | | /---------->|NOT|-->| |
SEL BUS -----/ ---------------------- PADR-->|AND| ---
4,2,1 \ |SECT 18:19 V A -W | WRITE ---
SEL BUS --\| |
------- 4,2,1 | 1K x 18 |
DEV 0 ->| | PADR 20:26 --/| RAM |
. | ADDR | / | MAPPED|
. | 14:35 |---> PADR MICRO 18:35 | ADDR |-->MAPRAM 14:26
. | SELECT| | 14:26|
DEV 7 ->| | ----------------------
---∧---
|
MICRQ SEL --/ --------
4,2,1 MAPRAM 14:26 -->|MEM ADDR|
| |-->PADSEL 14:26
-------- PADR 14:26 -->|SELETOR | PADR 27:35
RQ 0 -->| | --------
. | |---\ SEL BUS ---
. |PRIORITY|---/ 4,2,1 -PADR SUPRESS MAPPING -->| |
. | | -------
Registers and Tables
There are several 16 bit registers and a 16 word by 16 bit table in the
microprocessor. The registers are:
AR
BR
ALULAT
SEL BUS
PADR 18:26
PADR 27:35
and the table is PTPNT. These registers may be selected for reading and writing
by the microprocessor by means of certain bits and decodes of the microinstruction.
The data written into PTPNT is read out inverted.
FUNCTION BLOCKS
There are three major function blocks in the microprocessor; the S selector,
the masker and the ALU. They are all controlled by fields in the microword.
The S selector
The S selector selects one of eight 16 bit words for input to the rotator.
The inputs to the selector are:
PADR MICRO 18:26; MICRQ SEL 4,2,1; MS 0:3
MS 4:19
MS 20:35
-VBIT NEW BIT
-VBIT
PTPNT
AR
BR
The Masker
The masker performs selective byte substitution from one word into another.
The inputs to the masker are the output of the rotator, the mask generator
and the B selector. The B selector selects between the AR and BR under
microprogram control. The mask generator is a ROM which is addressed by 8
bits of the microinstruction; the mask size and the mask rotate. It produces
a consecutive string of ones of length "size" and rotates them left by the
amount "rotate". The rotator rotates the output of the S selector by an amount
specified in the microinstruction. The masker then produces an output
which selects the output of the rotator where the mask is a one and selects
the output of the B selector where the mask is a zero. The following equation
represents the operation of the masker for bit n:
mask output (n) = [mask (n) * rotate (n)] + [-mask (n) * B select output (n)]
The ALU
The inputs to tha ALU come from the A selector and the B selector. The A
selector selects either the output of the masker or the complement of a
16 bit constant from the microword. The function that the ALU performs is
under microprogram control.
INSTRUCTION FETCHING DATA PATHS
Instructions are fetched from either the 256 word instruction RAM or the
32 word instruction ROM and latched in the 32 bit instrcution register (IR).
Both memories are addressed by the output of the MPC selector called MPC A.
This selector selects either the output of the program counter (PC) or the
low 8 bits of the AR. This selector is not directly under the control of the
microprogram but rather is operated by the logic when the microcode attempts
to write into the microstore. The PC is an 8 bit counter which is
incremented after the fetch of each microinstruction in order to address the
next microinstruction. The PC is set to zero by resetting of the microprocessor
and may be set to an 8 bit value from the microinstruction when the microprocessor
executes a branch.
If the high order three bits of MPC A are all zero then the instruction is fetched
from the ROM, otherwise from the RAM. Currently there is no plan to use the first
32 RAM locations which are in the shadow of the ROM.
The data for writing into the RAM come from the low 32 bits of the MS. The
address for the RAM during writing always comes from the low 8 bits of the AR.
INSTRUCTION EXECUTION
Most instructions are executed in a single cycle of 130 nanoseconds.
Instructions are fetched from the microstore as addressed by the PC register
and latched in the IR. At the same time the PC is incremented to point to
the next consecutive instruction. By the time the current cycle ends, the
instruction RAM or ROM will have fetched the next microinstruction and be
ready to have it clocked into the IR. The IR is decoded to set up
the data paths and select inputs to the alu. The output of the alu goes back
to various registers and can be clocked into some of them at the end of the
cycle.
There are 8 possible opcodes of which there are 3 slightly different types.
Opcodes 0 and 3 through 7 set the A selector to the output of the masker and
specify a destination for the output of the ALU. Opcode 2 is like opcode
0 except that it specifies a 16 bit constant rather than rotate and masker
information and the A selector selects this constant rather than the output
of the masker. Opcode 1 is the conditional branch instruction. With this
opcode, the rotate and mask fields are specified but the destination and
ALU control fields are not. Instead, a branch condition and and a branch
address are specified. If, at the end of the microcycle, the branch condition
is not satisfied, then the next consecutive microinstruction is executed as
always. However, if the condition is satisfied, the next instruction is
fetched from the address specified in the microinstruction.
In the case where a branch is taken, the wrong instruction will have been fetched
ahead from the microstore. Therefore, an extra cycle is taken, which is wasted,
which allows the new value in the PC to address the microstore and fetch the
correct microinstruction.
In all opcodes except opcode 2 there is a bit which controls certain special
functions. In opcodes 0 and 1 a special function is performed only if the
bit is on. In opcodes 4 through 7 special functions are always performed and
the special function bit controls which one. Therefore, there are 10 possible
special functions.
Microword Formats
All microinstructions are of the following general 32 bit format:
0 2 3 18 19 30 31
--------- --------- --------- -------
| OP CODE | FIELD 1 | FIELD 2 | B SEL |
--------- --------- --------- -------
There are essentially three different instructions. These are determined
by the opcode field. Two of them are opcodes 1 and 2. Opcodes 0 and 3 - 7
represent the other instruction. The reason for having so many opcodes which
perform the same function is that in addition they each perform a different
special operation.
Opcodes 0, 3-7 Mask-ALU instruction
Opcode 1 Branch instruction
Opcode 2 Constant-ALU instruction
The decoding of Fields 1 and 2 depend upon the opcode.
Field 1 decoding for all opcodes except opcode 2:
Bits Name Function
3 IR SPEC 3 Perform special operation depending upon op code
4:6 IR S SEL 4,2,1 Controls 8 input S selector
7:10 IR M SIZE 7:10 4 of the address inputs to Mask Generate ROM
11:14 IR M ROT 11:14 4 more address inputs to the Mask Generate ROM
15:18 IR R ROT 15:18 Amount to rotate S by to produce R
The mask size field is -1 + the number of consecutive ones in the desired
mask.
Field 1 decoding for opcode 2:
Bits Name Function
3:18 IR CONST 3:18 16 bit constant which is complemented before being used
to produce A
Field 2 decoding for all opcodes except opcode 1:
Bits Name Function
19:24 IR ALU M 19 These 6 bits go to the ALU mode, function select and
-IR ALU S 20:23 carry-in inputs
-IR ALU CN 24
25:28 IR DEST 25:28 Destination decode
29 IR ARLD 29 Enable loading AR from ALU at the end of the instruction
30 IR BRLD 30 Enable loading BR from ALU at the end of the instruction
Field 2 decoding for opcode 1:
Bits Name Function
19:22 IR BR 19:22 Branch condition decode
23:30 IR ADDR 23:30 Branch address
S Selector Decodes
The field 1 S selector field decodes as follows:
IR S SEL 4,2,1 SELECTED SOURCE
0 AR
1 BR
2 PADR MICRO 18:26; MICRQ SEL 4,2,1; MS 0:3
3 MS 4:19
4 MS 20:35
5 -VBIT NEW BIT
6 -VBIT
7 PTPNT
Destination Decodes
The field 2 destination field decodes as follows:
IR DEST 25:28 DESTINATION
0 None
1 -SEL BUS REG
2 MA HI
3 MA LO
4 VBIT
5 ABIT
6 MAPRAM
7 -PTPNT
8 MAP ENB
Branch Conditions
The field 2 branch condition decodes as follows:
IR BR 19:22 BRANCH CONDITION EFFECT OF BRANCHING
OCT DEC
0 0 MCYC MEM DONE
1 1 -MCYC MEM DONE
2 2 MIOBC BUSY transfer I to MS
3 3 -MIOBC BUSY
4 4 RESET COND clear RESET COND
5 5 UNUSED
6 6 MCYC MASK = 0
7 7 -MCYC MASK = 0
10 8 -MASK BIT 0
11 9 MASK BIT 0
12 10 MPXERR MICRO RD PAR ERR clear MPXERR MICRO RD PAR ERR
13 11 UNUSED
14 12 TRUE (Always branch)
15 13 MICRQ RQ SYNC freeze MICRQ SEL synchronizer
16 14 UNUSED
17 15 UNUSED
Special Functions
The 10 possible special functions are as follows:
SPEC # OPCODE IR SPEC 3 FUNCTION
- 0 0 no special function
0 0 1 halt
- 1 0 no special function
1 1 1 unfreeze MICRQ SEL latch
2 2 - cannot perform special functions with this opcode
3 3 0 write MS in microstore at location addressed by AR
4 3 1 release control of SEL BUS and PADR 18:35; clear
PRIOR CYC IN PROG
5 4 0 get control of SEL BUS and PADR 18:35; set
PRIOR CYC IN PROG
6 4 1 same as above but also begin mem read cycle
7 5 0 clear CYSTAT START n
10 5 1 clear MIOBC BUSY
11 6 0 set PT PAR ERR for device MICRQ SEL 4,2,1
12 6 1 set MPXERR PAR ERR during u-code read
13 7 0 clear MCYC MEM DONE
14 7 1 clear MICRQ for device = MICRQ SEL 4,2,1
I/O Bus Interface
The Mappiplexor's I/O Bus device code is 530 symbolic name MPX.
CONO MPX,E
Bit Function
18d Clear access violation
19d Clear write violation
20 Clear MPX NXM
21 Clear MPX PAR ERR
*22 Reset MPX (don't turn on any other CONO bits with this one)
*23d Reset device
24:26 Device code
27d Clear PT PAR ERR (page table parity error)
28d Clear WRITE PAR ERR
29d Clear READ PAR ERR
*30d Disable mapping
*31d Enable mapping
32 Enable load PIA
33:35 PIA
* indicates that BUSY will be set as a result of the CONO. BUSY
will be cleared after the specified operation is completed.
d indicates that the operation is performed for the device whose number is in
the device code field (bits 24:26).
*DATAO MPX,E
Bit Function
0 1 if DATAO is for loading microcode, 0 if for loading a page table pointer
1 ignored
If bit 0 = 0
15:17 Device code
23:35 Page table pointer (page number of page table)
If bit 0 = 1
23:35 Page number of first word of microcode
* again indicates that any DATAO will cause BUSY to be set. BUSY will be
cleared when the operation is complete.
CONI MPX,E
Bit Meaning
13+N*2 Device N access violation
14+N*2 Device N write violation
29 BUSY
30 MPX is interrupting
31 MPX NXM
32 MPX PAR ERR
33:35 PIA
DATAI MPX,E
Bit Meaning
12+N*3 Device N PT PAR ERR
13+N*3 Device N WRITE PAR ERR
14+N*3 Device N READ PAR ERR
When an I/O Bus instruction is executed which sets MIOBC BUSY
(indicated by a * in the above descriptions), a register called I 0:35
is loaded. Bits 0 and 2:35 are loaded from the I/O Bus data lines,
while bit 1 depends upon the particular instruction executed.
If the instruction is a CONO, then bit 1 is loaded with a zero.
If the instruction is a DATAO, then bit 1 is loaded with a one.
Mappiplexor Bus Interface
The connection of an external device to the mappiplexor is
accomplished over a TTL bus which is similar in some respects to a
UNIBUS. The bus consists of address bits, bidirectional data bits
and four control bits. All signals on the bus are active low and
should be terminated at the receiving end. (i.e., the mappiplexor
already terminates those signals it receives and any device on the
bus should do likewise.) The termination should be 220 ohms to +5V
and 330 ohms to ground. Unidirectional bits may be driven with a
7437, 74S37 or 8T96 type driver. Bidirectional bits may be
transceived with an 8T26.
The signals on the bus are the following:
- MA 14 through - MA 35 (to MPX)
- D 0 through - D 35 (bidi)
- PARITY (bidi)
- REQUEST (to MPX)
Detailed Logic Description - Microprocessor Data Paths and Registers
Print pages: MICBUS, ALULAT, ALU, A, MASK, M, R, B, S, AR, BR, PTPNT, I, MS
The S page contains a 16 bit 8 input selector whose output is called S 0:15.
The inputs are described on page 6 under "S Selector Decodes." The selection
is determined by a three bit microcode field. The output of the S selector
is sent to the rotator on the R page. The rotation is done in two levels.
The first level rotates the 16 bit S word bF≥G]Xas REQUEST is asserted. When REQUEST is dropped
both DONE and read data will be dropped and a new cycle can begin
any time thereafter.
Ordinarily, the mappiplexor will map MA 18 through MA 35 into a 22
bit physical address according to the page table in effect for the
device at the time of the request. However, if the SUPPRESS MAPPING
signal is asserted with the request, then the address will not be
mapped and the full 22 bit device generated address (MA 14 through MA
35) will be sent to the memory. This may be used, for example, by a
channel that fetches commands from memory and wishes those references
to be unmapped.
MAPPIPLEXOR BUS - QUICKLATCH CONNECTOR
FC PIN QL PIN QL GND SIGNAL
A1 D A1 B1 -DONE
A1 E A2 B1 unused
A1 H B2 A3 unused
A1 K B3 A3 -PARITY
A1 M A4 B4 -REQUEST
A1 P A5 B4 unused
A1 S B5 A6 unused
A1 T B6 A6 -MA 18
A1 V A7 B7 unused
B1 D C1 D1 -MA 19
B1 E C2 D1 unused
B1 H D2 C3 -MA 20
B1 K D3 C3 -SUPPRESS MAPPING
B1 M C4 D4 -MA 14
B1 P C5 D4 -MA 15
B1 S D5 C6 -MA 16
B1 T D6 C6 -MA 17
B1 V C7 B7 unused
A2 D E1 F1 -MA 22
A2 E E2 F1 -MA 23
A2 H F2 E3 -MA 24 ------ ------
A2 K F3 E3 -MA 25 | 1 2 | | 3 4 |
A2 M E4 F4 -MA 26 | | | |
A2 P E5 F4 -MA 27 | A A | | A A |
A2 S F5 E6 -MA 28 | | | |
A2 T F6 E6 -MA 29 | B B | | B B |
A2 V E7 F7 -MA 30 ------ ------
B2 D H1 J1 -MA 31
B2 E H2 J1 -MA 32
B2 H J2 H3 -MA 33
B2 K J3 H3 -MA 34
B2 M H4 J4 -MA 35 WIREWRAP SIDE
B2 P H5 J4 unused
B2 S J5 H6 -WRITE
B2 T J6 H6 unused
B2 V H7 F7 -MA 21
1 2 3 4 5 6 7
A3 D K1 L1 -DATA 00
A3 E K2 L1 -DATA 01 A A A A A A A
A3 H L2 K3 -DATA 02 B B B B B B B
A3 K L3 K3 -DATA 03 C C C C C C C
A3 M K4 L4 -DATA 04 D D D D D D D
A3 P K5 L4 -DATA 05 E E E E E E E
A3 S L5 K6 -DATA 06 F F F F F F F
A3 T L6 K6 -DATA 07 H H H H H H H
A3 V K7 L7 -DATA 08 J J J J J J J
K K K K K K K
B3 D M1 N1 -DATA 09 L L L L L L L
B3 E M2 N1 -DATA 10 M M M M M M M
B3 H N2 M3 -DATA 11 N N N N N N N
B3 K N3 M3 -DATA 12 P P P P P P P
B3 M M4 N4 -DATA 13 R R R R R R R
B3 P M5 N4 -DATA 14 S S S S S S S
B3 S N5 M6 -DATA 15 T T T T T T T
B3 T N6 M6 -DATA 16
B3 V M7 L7 -DATA 17
A4 D P1 R1 -DATA 18
A4 E P2 R1 -DATA 19
A4 H R2 P3 -DATA 20 Note: Pins D7, J7, N7 and T7 have
A4 K R3 P3 -DATA 21 no wires connected in the
A4 M P4 R4 -DATA 22 cable.
A4 P P5 R4 -DATA 23
A4 S R5 P6 -DATA 24
A4 T R6 P6 -DATA 25
A4 V P7 R7 -DATA 26
B4 D S1 T1 -DATA 27
B4 E S2 T1 -DATA 28
B4 H T2 S3 -DATA 29
B4 K T3 S3 -DATA 30
B4 M S4 T4 -DATA 31
B4 P S5 T4 -DATA 32
B4 S T5 S6 -DATA 33
B4 T T6 S6 -DATA 34
B4 V S7 R7 -DATA 35
Error Conditions
y 0, 4, 8 or 12 bits according to
the high order two bits of the rotate value. The resulting word is rotated
by 0, 1, 2 or 3 bits according to the low order two bits of the rotate value
to produce the rotator output, R 0:15.
The M page contains a 256 word by 16 bit read only memory. The eight address
bits come from a microcode field and have the following interpretation. The
high order 4 bits specify a size. Values 0 through 15 give a number of one
bits from 1 to 16. The low four bits specify a rotation amount from 0 to 15.
Rotation of 0 leaves the one bits right adjusted in the 16 bits word. The M
output word is called M 0:15
The AR and BR pages contain the 16 bit registers of the same name. They are
loaded from the output of the ALU when enabled by individual microcode bits,
MCYC ARLD ENB for the AR and MCYC BRLD ENB for the BR.
The B page contains a selector whose output, B 0:15 is connected to the B input
of the ALU. The B selector is controlled by a microcode bit and selects between
the AR and the BR.
The MASK page contains 16 2-input selectors, implemented with and-or-invert
gates. One selector input is R 0:15, the output of the rotator, and the other
input is B 0:15, the output of the B selector. The selection for each bit
is determined by the M output, M 0:15. The R input is selected when the
corresponding M bit is high and the B input is selected when the M bit is low.
The output of these selectors is active low and called -MASK 0:15.
The A page consists of a selector which chooses between the MASK output and
a 16 bit microcode field depending on the microinstruction opcode. The output
of the selector is called A 0:15 and goes to the A input of the ALU. The selector
is inverting and therefore inverts the 16 bit microcode field or re-inverts the
-MASK word to make it active high.
The ALU is a standard 74S181 connected with a carry lookahead generator. The
mode, function select and carry in bits all come from the microinstruction.
The output of the ALU is called ALU 0:15 and is the source of all data for loading
into microcomputer registers. The ALU output also goes to the ALULAT page where
it is loaded at the end of every microinstruction. This preserves the ALU data
generated in the current microinstruction for writing into RAMs during the next
microinstruction.
The MICBUS page contains three registers which are implemented with AMD 25S18s.
These parts are 4 bit D type flip flops with totem pole and tri-state outputs.
The three registers are the SEL BUS, PADR 14:26 (also called MA HI) and
PADR 27:35 (also called MA LO). The tri-state outputs are connected in
parallel with the signals of the same name generated by the priority logic
and the address selectors. These registers are loaded from the ALU output
when addressed by the microinstruction destination field. The tri-state output
enable on these registers is controlled by a signal from the priority logic
which determines that the microprocessor rather than the address receivers should be
driving the SEL BUS and PADR lines.
The PTPNT page has the 16 word by 16 bit page table pointer register and its
address selector. The output of the RAM, PTPNT 0:15 goes to the S selector and
its input comes from the ALULAT register. The address to the PTPNT RAM comes
from the low order 4 AR bits of the AR for writing and from the microprocessor
request logic for reading.
The I page contains the I register which is loaded with received I/O bus data
on DATAO and certain CONO instructions. The output of the I register, I 0:35
goes to one input of the MS selector/register. The other input comes from the
memory interface and is the result of the last read cycle. The MS register is
loaded either when the read data is available from the memory interface (loads
from MEMDON D 0:35) or when the microprocessor successfully branches on MIOBC
BUSY (loads from I 0:35).
Detailed Logic Description - I/O BUS Interface
Print pages: RIOBC, RIOBD, DIOBD, MIOBC, I
The I/O Bus is transceived with SC level converters on the RIOBC and RIOBD
pages. The MIOBC page generates the appropriate I/O Bus pulses when the
Mappiplexor device code is selected (530). The page contains the PIA register
and the PI decoder for generating interrupts. The MIOBC BUSY flip flop is
set by any DATAO instruction or any CONO with bits 22, 23, 30 or 31 on.
This flip flop is a branch condition that is looked at by the microprocessor
in its idle loop. The setting of the MIOBC BUSY flip flop also clocks the
I register. Bits 0 and 2:35 are loaded from the received I/O Bus data.
Bit 1 is loaded from a flip flop called MIOBC 1. This flop is set by DATAO
and cleared by CONO and gives the microprocessor an indication of which type
of instruction caused MIOBC BUSY to be set. MIOBC BUSY is cleared by microcode
special function 10. When the microcomputer branches successfully on MIOBC BUSY,
the I register is transferred into the MS register where the microcomputer can
access it.
Detailed Logic Description - Clock Generation